D21m System
D21m Modules 6-11Date printed: 30.08.07
Input / output impedance 110 Ω
Input sensitivity min. 0.2 V
Output level (into 110 Ω) 5 V
SFC range 22...108 kHz
Current consumption (3.3 V) 1.949.422: 0.2 A; ..423: 0.4 A; ..424: 0.6 A
(5 V) 0.65 A
Operating temperature 0...40° C
Input SFC*
Enabled
Bypassed
*
1.949.423 and 1.949.424 only
**
1.949.424 only (see Note 1)
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
Ch 8
Output Word Length**
24 Bit 20 Bit
18 Bit 16 Bit
Output Sampling Rate**
Ch 4
Ch 3
Ch 8
Ch 7
Ch 6
Ch 5
Ch 2
Ch 1
Ch 5...8
Ch 1...4
Ch 5...8
96 k Ext.
Output SFC**
Bypassed
Enabled
Ch 1...4
48 k 44.1 k
LEDs: LOCK 1...8 These green LEDs are on if a valid AES/EBU signal is available at the
inputs.
Jumpers:
Input SFC Enabling or bypassing of the SFCs for individual AES/EBU input channels.
Output Sampling frequency (1.949.424 only) The output sampling frequency may be set for the AES/
EBU output channel groups 1...4 and 5...8; selection from 44.1 kHz, 48 kHz,
96 kHz, or synchronized by the signal at the AES EXT SYNC IN connector
(see “Note” above).
If no valid signal is provided at the AES EXT SYNC IN connector but Ext.
is selected, the output sampling frequency will be set to the system clock.
Outputs set to Ext. can therefore be used in a very exible way: Connect no
external sync signal, if not necessary, so that the output will be clocked with
the internal system clock. As soon as an external sync signal is provided to
the AES EXT SYNC IN connector, the output will be clocked with the ext.
sync signal.
Output SFC / WL Reduction (1.949.424 only) Enabling/bypassing of the output SFCs, separate for the
AES/EBU output channel groups 1...4 and 5...8. Please note that for word
length reduction the output SFCs must be set to Enabled.
